In recent years, the microprocessing technology is progressing for achieving higher speed and higher degree of integration of a semiconductor integrated circuit device. Along with this, variations in process, voltage and temperature (PVT) affect device characteristics more remarkably, and accordingly the technology of controlling an influence on the characteristics in an entire circuit against such variations becomes more and more important. Moreover, driving voltage becomes reduced along with the advance of technology, which results in a further increase in fluctuations of device characteristics which result from variations in PVT.
Against this background, a silicon-on-insulator (SOI) device is receiving attention in recent years. Particularly in the area of mobile devices, it becomes extremely important to reduce voltage and power consumption without sacrificing required performance. Under the circumstances, a limitation is being posed on scaling of a threshold value in a bulk silicon device, and hence it is difficult to make improvement in performance and operation with reduced power consumption compatible with each other in terms of leakage current.
For this reason, in the SOI device, a MOS transistor is formed on a thin silicon single crystal layer (SOI layer) disposed on a silicon oxide film (buried oxide film). As a result, not only side surfaces but also a bottom surface of a transistor active region is covered with the silicon oxide film. Therefore, compared with a MOS transistor formed on a bulk silicon substrate, PN junction area is reduced, and parasitic load capacitance is reduced by a larger amount, which enables high-speed operation and low-consumption-power operation.
This SOI device has a characteristic that a channel region (hereinafter, referred to as floating body, or merely as body) of a transistor is brought into an electrically floating state. One whose floating body is fully covered with a depletion layer during operation is referred to as a fully-depleted transistor, whereas one whose floating body includes a remaining region which is not depleted during operation is referred to as a partially-depleted transistor.
As to a partially-depleted transistor, for example, Patent Document 1 discloses a method of forming transistors having threshold values different from each other.
The partially-depleted transistor is only required to be formed on an SOI layer which is relatively thick, and thus has a characteristic that it is manufactured relatively with ease because substantially the same process as a typical bulk CMOS process is applied thereto.
Further, in the partially-depleted transistor, there is frequently used a mode of fixing a body potential by attaching an electrode to a body (body-fixing) to be used in a substrate-fixed mode similar to that of the bulk device. In this case, though static characteristics of the transistor are substantially the same as those of the bulk CMOS device, there is an advantage that it is possible to use the same platform (EDA tool, setting environment, library and IP) as that of the bulk CMOS device. Further, there is another advantage that the partially-depleted transistor operates at speed higher than the bulk CMOS device by 10 to 20% because an effect of reducing a parasitic capacitance is the same as that of the SOI device.
In contrast, in the fully-depleted transistor, there is no parasitic substrate capacitance below a gate electrode because a body is fully depleted, and thus speedup is expected further. However, the fully-depleted transistor needs to be formed on a thin SOI layer for fully depleting the body, and thus is not put to practical use from the viewpoints of processing technology and the like.
Patent Document 2 discloses a transistor which is brought into a fully-depleted mode during a circuit operation during which an ON state and an OFF state are repeated and brought into a partially-depleted mode during stand-by operation, in which switching between the modes is controlled by a voltage applied to a back gate electrode.
Patent Document 1: Japanese Patent Application Laid-Open No. 2002-16260 (FIGS. 4 and 5)
Patent Document 2: Japanese Patent Application Laid-Open No. 11-261072